The present invention relates to semiconductor devices and manufacturing methods therefor, and more particularly, to a technique suitable for use in a semiconductor device including copper redistribution lines.
To address the downsizing of electronic devices and the like, wafer-level chip-scale packaging technology has been increasingly developed in the field of semiconductor devices. Wafer-level chip-scale packaging is a technology that involves performing a series of processes for forming elements, the wiring, and the like over a semiconductor substrate (wafer), followed by forming a passivation film, and then forming more wiring, electrodes (pads), and the like over the passivation film.
The wiring formed over the passivation film is referred to as a redistribution line. The size of the redistribution line is approximately an order of magnitude larger than that of a normal wiring formed under the passivation film. A material suitable for use in the redistribution line is copper, which has a relatively low electric resistivity (specific resistance) and a high thermal conductivity.
A bonding pad for bonding a copper wire is formed at the surface of the redistribution line. As the bonding pad, a gold (Au) film or the like is formed. Such a structure that has the bonding pad including the gold film in the redistribution line is called a “redistribution layer with Au pad (RAP) structure”.
After forming the bonding pads, a polyimide film is formed to cover the redistribution lines, the bonding pads, and the like. The polyimide film is provided with an opening for exposing each bonding pad. Thereafter, the wafer is diced into chips. A copper wire is bonded to the bonding pad of a semiconductor device of the chip, and then the semiconductor device (chip) is sealed (packaged). Note that Patent Document 1 is an example of a document that discloses a general copper wiring.